With SOI (silicon-on-insulator) technology, a thin silicon layer is formed over an insulating layer, such as silicon oxide, which in turn is formed over a bulk substrate. The insulating layer is referred to as a BOX (buried oxide) layer. For a single BOX SOI wafer, the thin silicon layer is divided into active regions using STI structures, which intersect the BOX layer. In general, the STI structures are fabricated by etching a pattern of trenches in the SOI substrate below the BOX layer, and depositing one or more layers of dielectric material to fill the trenches. The STI structures define the active regions, and provide isolation between active regions in the upper silicon layer of the SOI in which devices such as FETs (field effect transistors) are formed. The gate structures of FETs are formed on top of the thin silicon layer, for example, by depositing a gate dielectric layer and a gate electrode layer on the top surface of the thin silicon, followed by photolithographic patterning, and etching to form gate stack structures. The sources and drains of field effect transistors are then formed, for example, by ion implantation of N-type and/or P-type dopant material into the thin silicon layer using a gate stack structure to self-define a channel region.
In a single BOX SOI structure, the silicon layer underlying the BOX layer can be used as a back gate layer under the active regions, wherein the BOX layer serves as the back-gate dielectric, wherein the back gate can be defined by either P+ or N+ implantation. FETs with back gates typically use a UTBB (Ultra-Thin Body and Box) substrate having a relatively thin upper silicon layer and thin BOX layer to enable fully depleted device operation with a threshold voltage that is responsive to a back gate voltage applied to the back gate (lower silicon layer). FETs fabricated using UTBB technology with back gates have significant advantages such as, for example, reduced short channel effects, less threshold variability due to body doping fluctuations, and ability to use the back gate voltage to adjust the threshold voltage
However, as the thickness of the BOX layer is reduced for UTBB structures, the potential for electrical shorts between the upper and lower silicon layers of the device increases as a result of various processing steps that can etch down the trench fill material and expose the upper and lower surfaces of the upper and lower silicon layers on the sidewalls of the shallow trench.